1. Field of Invention
The present invention relates to a method of forming a contact in semiconductor device, more particularly, to a method of forming a tungsten bitline contact in a semiconductor device which prevents the decrease of impurity ion density in an impurity region and reduces both contact resistance between a plug and the impurity region and leakage current in a junction by forming an extra barrier layer in a metal barrier layer having been deposited on the impurity region, thereby improving operation speed of a semiconductor device and lessening power consumption.
2. Discussion of Related Art
It is very important to design a circuit of low power consumption and high operation speed as the density of semiconductor becomes higher rapidly. One of limitations required for designing such a circuit of low power consumption is the reduced contact resistance.
A major study for increasing the integration and operating speed in a memory device is the technique of forming plug and bitline with tungsten. This technique is essential to the fabrication of a high performance memory device as specific electric resistance of this structure is one-eighth less than that of the tungsten-polycrystalline silicon.
In the contact area of a tungsten bitline according to a related art, the impurity region of source and drain is doped with B, the metal barrier layer is made of TiN and the plug is formed with tungsten(W).
B tends to diffuse into metal, i.e. TiN and W, at a high temperature over 700.degree. C. After a bitline has been formed with W, impurity ions having been buried in source/drain regions diffuse into the TiN and W layers during the following steps for capacitor fabrication, insulating interlayer deposition, thermal treatment and the like, wherein W has the highest tendency in diffusion.
Then, the density of B of a dopant in the impurity diffusion region of a substrate decreases, while the contact resistance increases. Thus, power consumption of a device increases and operation speed becomes slow.
A plug of W is formed by flowing gases such as WF.sub.6 on a barrier metal layer preventing diffusion by chemical vapor deposition(hereinafter abbreviated CVD) to fill up a contact hole.
Having been contained in the plug, F out of WF.sub.6 diffuses into an interface between Si and TiSi.sub.x at a surface of the silicon substrate to form TiF.sub.x and penetrates into the source/drain junction deep. Thus, contact resistance and junction leakage current increase.
When heat treatment to form TiSi.sub.x of silicide is carried out on a substrate, the volume of TiN which is a barrier metal layer at the lower part of a contact hole is larger than that of TiSi.sub.x which is silicide. Thus, micro-cracks are brought about by the stress caused by the reduced volume when TiSi.sub.x is formed.
FIGS. 1A to FIGS. 1C show cross-sectional views of forming a contact in a semiconductor device according to a related art.
Referring to FIGS. 1A, an insulating interlayer 12 is formed by depositing an oxide or nitride layer on a semiconductor substrate 10, in which a p-typed impurity diffusion region 11 having been heavily doped with B to form source and drain, by CVD.
The insulating interlayer 12 is coated with photoresist. Then, a photresist pattern exposing the portion of the insulating interlayer 12 over the contact area to be opened is formed by exposure and development of the photoresist.
A contact hole exposing a portion of the impurity diffusion region 11 is formed by removing the portion of the insulating interlayer which is not covered with the photoresist pattern. In this case, a bitline contact including a plug is to be formed in the contact hole.
A natural oxide layer on the impurity diffusion region 11 of the substrate which is exposed by the formation of the contact hole and polymers having remained in the contact hole are removed by a cleaning process with HF or BOE.
Referring to FIGS. 1B, a Ti layer 13 is formed on the remaining insulating interlayer 12 and the exposed impurity diffusion region 11 to form a silicide layer. And, a TiN layer 14 as a barrier metal layer 14 which prevents diffusion is deposited on the Ti layer 13. In this case, each of the metal layers 13 and 14 is formed by sputtering to be about 300 .ANG. thick. The sputtering method uses one of Collimated Ionized Metal Plasma or Hollow Cathode Magnetron according to the aspect ratio of the contact hole.
A silicide layer 15 of TiSix, which is generated from the reaction between Ti and Si and reduces contact resistance, is formed at an interface between the Ti layer 13 and the impurity diffusion region 11 by carrying out thermal treatment on the surface of the substrate 10 at a temperature over 650.degree. C. under nitrogen ambience. In this case, the thermal treatment is carried out by a rapid thermal process for about 30 seconds or put in the furnace for about 30 minutes.
Referring to FIGS. 1C, a tungsten layer about 4000 .ANG. thick is formed by CVD on the barrier metal layer 14 to fill up the contact hole.
Then, a tungsten plug 16 filling up the contact hole is formed by planarizing the tungsten layer by etchback or chemical-mechanical polishing(hereinafter abbreviated CMP) until the surface of the barrier metal layer 14 is exposed.
Another tungsten layer about 1000 .ANG. thick is deposited on the barrier metal layer 14 including a surface of the exposed plug 16 by CVD or sputtering.
A bitline 17 is defined by patterning the tungsten layer on the barrier metal layer 14 by photolithography.
Unfortunately, relating to the method of forming a bitline contact in a semiconductor device according to the related art, the density of B of a dopant in the impurity diffusion region of a substrate decreases, while the contact resistance increases. Thus, power consumption of a device increases and operation speed becomes slow.
And, having been contained in the plug, F out of WF.sub.6 diffuses into an interface between Si and TiSi.sub.x at a surface of the silicon substrate to form TiF.sub.x and penetrates into the source/drain junction deep. Thus, contact resistance and junction leakage current increase.
Moreover, when heat treatment to form TiSi.sub.x of silicide is carried out on a substrate, the volume of TiN which is a barrier metal layer at the lower part of a contact hole is larger than that of TiSi.sub.x which is silicide. Thus, micro-cracks are brought about by the stress caused by the reduced volume when TiSi.sub.x is formed.